View Issue Details
| ID | Project | Category | View Status | Date Submitted | Last Update |
|---|---|---|---|---|---|
| 0000456 | T99X171.00 SKB Eagle | HW | public | 2019-02-19 17:37 | 2019-04-24 09:55 |
| Reporter | Assigned To | Due Date | 2019-02-21 18:31 | ||
| Priority | immediate | Severity | s3-moderate | Reproducibility | N/A |
| Status | closed | Resolution | fixed | ||
| Summary | 0000456: DDR SI Simulation report | ||||
| Description | SKB request to DDR SI simulation report. If you cannot prepare the report, please let me know the due date | ||||
| Tags | No tags attached. | ||||
| Attach Tags | |||||
| User List |
|
|---|
|
|
I reviewed the SI simulation data But, DDR memory is SK Hynix. I said the document is OK at CC, but I need to the SI simulation document of Samsung DDR. SKB request SI simulation test. So you plan to SI simulation and test. If Amlogic lead to SI simulation, please co-work and support. |
|
|
Reminder sent to: (HW) Sean Chiang, (PM) Sheila Tu, (SW) Jacky Chiang, (SW) Kerwin Chen |
|
|
Both Amlogic and FXN can do the DDR SI simulation. Amlogic reply us the DDR SI simulation will be scheduled to beginning of March and estimated to finish by mid. of March We are checking with FXN DDR SI team to see if FXN can do to shorten the schedule |
|
|
FXN DDR SI team can do the simulation and the report can be provided beofre 3/6 |
|
|
ok. thank you |
|
|
Hi SB, Update DDR SI simulation report as attached. |
|
|
Hi Sean. 1. according to page3, you add the jedec spec. but the jedec spec in report shows 1600~2400Mbps. Eagle DDR speed is 2666MHz as you know 2. You gave the Hynix SI simulation report "FOXCONN_S905X2_DDR4_2666_Simulation_Report_20191227.docx" at 19th Feb. That report is more visible than Samsung SI simulation. Could you change Samsung DDR si report format to Hynix report format? |
|
|
Hi SB, 1. according to page3, you add the jedec spec. but the jedec spec in report shows 1600~2400Mbps. Eagle DDR speed is 2666MHz as you know Sean: We will update report to you later. 2. You gave the Hynix SI simulation report "FOXCONN_S905X2_DDR4_2666_Simulation_Report_20191227.docx" at 19th Feb. That report is more visible than Samsung SI simulation. Could you change Samsung DDR si report format to Hynix report format? Sean: Sorry, since the Hynix SI simulation report was done by Amlogic but Samsung is done by FXN team. We may ask Amlogic to do DDR SI simulation again but it might take long time to complete it since Amlogic is lack resource to do this task. |
|
|
Hi Sean Please update progress of DDR SI |
|
|
Hi SB, We already receive the jedec spec. of 8Gb DDR4 (2666Mbps) from Samsung but the 4Gb is not ready yet mentioned by Samsung's local distributor. We will keep pushing Samsung to send us jedec spec. and will update the report to you once we got any update from vendor. For report format, since the previous Hynix SI simulation report was done by Amlogic. And the Samsung's DDR SI was done by FXN internal team. So, we can not change Samsung DDR si report format to previous Hynix report format. |
|
|
Hi Jim, Please track this issue with FXN SI team and update the report when you get update from FXN SI team next week. |
|
|
Hi SB Update report |
|
|
Thank you Jim |
| Date Modified | Username | Field | Change |
|---|---|---|---|
| 2019-02-19 17:37 |
|
New Issue | |
| 2019-02-19 17:37 |
|
Status | new => assigned |
| 2019-02-19 17:37 |
|
Assigned To | => (HW) Sean Chiang |
| 2019-02-20 21:54 |
|
Note Added: 0001174 | |
| 2019-02-20 21:59 |
|
Issue Monitored: (ALTech) SB Park | |
| 2019-02-20 22:03 |
|
Issue Monitored: (ALTech) SY Yoon | |
| 2019-02-22 10:35 |
|
Issue Monitored: (PM) Sheila Tu | |
| 2019-02-22 10:35 |
|
Issue Monitored: (SW) Jacky Chiang | |
| 2019-02-22 10:35 |
|
Issue Monitored: (SW) Kerwin Chen | |
| 2019-02-22 10:35 |
|
Note Added: 0001175 | |
| 2019-02-22 16:37 | (HW) Sean Chiang | Status | assigned => feedback |
| 2019-02-22 16:37 | (HW) Sean Chiang | Note Added: 0001189 | |
| 2019-02-25 18:24 | (HW) Sean Chiang | Note Added: 0001196 | |
| 2019-02-25 21:08 |
|
Note Added: 0001197 | |
| 2019-02-25 21:08 |
|
Status | feedback => assigned |
| 2019-03-06 20:27 | (HW) Sean Chiang | File Added: T99X171T00_SI-PostSIM-DDR4-2666_V20190306.pdf | |
| 2019-03-06 20:27 | (HW) Sean Chiang | Note Added: 0001375 | |
| 2019-03-06 22:25 |
|
Note Added: 0001381 | |
| 2019-03-08 20:47 | (HW) Sean Chiang | Note Added: 0001427 | |
| 2019-03-19 21:48 |
|
Note Added: 0001619 | |
| 2019-03-29 20:05 | (HW) Sean Chiang | Note Added: 0001777 | |
| 2019-04-03 20:22 | (HW) Sean Chiang | Assigned To | (HW) Sean Chiang => (HW) Jim Liang |
| 2019-04-03 20:27 | (HW) Sean Chiang | Note Added: 0001868 | |
| 2019-04-08 14:36 |
|
File Added: T99X171T00_SI-PostSIM-DDR4-2666_V20190325.pdf | |
| 2019-04-08 14:36 |
|
Note Added: 0001903 | |
| 2019-04-08 23:11 |
|
Note Added: 0001914 | |
| 2019-04-24 09:55 |
|
Status | assigned => closed |
| 2019-04-24 09:55 |
|
Resolution | open => fixed |
